A buck DC-DC converter 101 is constructed from two switches, a series switch SW1 and a shunt switch SW2, with an inductor (LOUT) connected to the node (VSW) between the two switches (FIG. 1). In pulse-width-modulated (PWM) operation, during each switching cycle, the series switch SW1 is turned on for a period TSW1=DTsw, where D is the duty cycle and Tsw is the switching period (FIG. 2). As depicted series switch state 210, the series switch SW1 is then turned off and as depicted by the shunt switch state 220 the shunt switch SW2 is turned on for a time TSW2=(1−D)Tsw−Tdead, where Tdead is the dead time during which both switches are held off (Dead times are interposed to ensure that the two switches (SW1, SW2) are not on simultaneously, which would permit current to flow directly from the supply to ground, with consequent excessive power dissipation and possible reliability impairment.) The output voltage of an ideal converter is DVIN, where VIN is the input supply voltage. In a real converter, the output voltage is reduced from the ideal value due to the presence of finite parasitic resistance, inductance, and capacitance.
When the converter is to operate at output voltages close to the input voltage, D must approach 1. As a consequence, the shunt switch on-time TSW2 becomes much shorter than the series switch on-time TSW1. In particular, in a high-speed converter, in which the switching period may be reduced to some tens of nanoseconds, very short values of TSW2 must be supported to achieve output voltage close to the input voltage. For example, if a switching frequency fSW of 35 MHz is employed, the switching period is 28 nanoseconds. To produce an output voltage of 3.4 V from an input voltage of 3.7 V, with output currents appropriate to the requirements of an RF power amplifier in a mobile radio transmitter, will require a duty cycle of about 95%. An ideal converter operating at a duty cycle of 95%, with dead times of 300 picoseconds preceding the turnon of SW1 and SW2, requires an on-time of (0.05)(28)−0.6=0.8 nanosecond for SW2. The PWM controller must produce a very short pulse, which must then be conveyed with good fidelity through a driver amplifier to drive a large switching transistor.
An exemplary buck converter is depicted in more detail in FIG. 3. The PWM Controller 310 comprises an error amplifier 320 with frequency-dependent compensation 330 and 335, to enable the converter to adjust the duty cycle for the desired output voltage while maintaining stable operation. The error amplifier output is compared by comparator 315 to a sawtooth waveform 325 to produce a timing pulse Vt, which is used by a Timing Block 340 to produce the series and shunt control signals. The timing block may be a simple exclusive-or function that turns the shunt switch off when the series switch is on, or various more elaborate schemes may be used to control relative timing of the series and shunt switches. The resulting output signals generally require amplification before they can be used to control the state of the relatively-large switching transistors. As depicted schematically in FIG. 3, a typical driver amplifier of a switch block 350, such as 355 or 360, consists of a cascade of inverters, each larger than the previous, such that the first stage can readily by driven by a digital control circuit, and the final stage is sufficiently large to drive the capacitance of a switching transistor with a periphery of several millimeters. Each inverter stage has a strongly nonlinear response, such that for a wide pulse, the rising and falling edges of the pulse are sharper at the output of the inverter than they were at the input, until they are limited by the minimum rise and fall times of the inverter stages. This nonlinear response is normally beneficial, but as a consequence, very short pulses may disappear altogether within the inverter chain. Thus, the relationship between the width of the pulse sent into the driver amplifier, and the width of the pulse delivered to the gate of the switching transistor, may incorporate an abrupt step to zero output pulse width at a finite input pulse width. The switching node potential VSW may still fall when the series switch turns off, even if the shunt switch does not turn on, due to the current flowing through the output inductor, which cannot change rapidly. However, if the OFF pulse to the series switch driver 355 is partially or completely lost, the series switch will remain ON, giving rise to a sudden upward step in output voltage as a function of nominal duty cycle.
Such an abrupt step gives rise to undesired control behavior. For target voltages in the region of D between the shortest pulse that is successfully transmitted through the driver amplifier, D=DMAX, and D=1, an oscillation may occur. This oscillation can be regarded as a limit cycle behavior between a first condition where SW1 is always on and SW2 is always off, which will produce a relatively high output voltage, and a second condition where SW1 is off and SW2 is on for a relatively long time corresponding to D=DMAX, producing a relatively low output voltage. The relative time spent in each condition will be adjusted to produce the desired average output voltage, but alternation between the low-D and high-D operating conditions results in oscillations in the output voltage when averaged over a few switching cycles.
An example of such an undesired oscillation is depicted in FIG. 4A and FIG. 4B, which depict measured data for an integrated circuit implementation. In this example, the converter is operating at a nominal switching frequency of about 32 MHz. When the output voltage is set to about 3.3 V for an input voltage of 3.7 V (conversion ratio of 89%), an oscillation can be seen in the output voltage 410 (FIG. 4A), with amplitude roughly 100 mV peak-to-peak at about 8 MHz (fsw/4). Examination of the switching node voltage VSW (420 in FIG. 4B) reveals that the converter is alternating between two operating modes: one in which switching proceeds normally, with SW1 turning off and the node voltage falling towards ground during each 30-ns switching cycle, and a second mode in which SW1 is ON throughout the normal 30-ns switching cycle. The net result is a disturbance at an effective frequency of around 8 MHz. Since this is only slightly above the frequency at which an envelope tracking converter must intentionally vary its output, the output filter provides only moderate rejection, and the resulting spurious frequency may appear in the output of a power amplifier connected to the converter.
Such limit cycle oscillations are known in digitally-controlled converters, where they typically result from a discrepancy in the resolution of the analog-digital conversion of the sensed voltage and that of the pulse-width-modulation controller. When objectionable in the application, oscillations are avoided by appropriate control of the converter resolutions and controller bandwidth. Limit cycle oscillations may be intentionally induced and employed for compensator optimization. Oscillations have also been reported in analog-controlled buck/boost converters. Oscillation suppression methods described to date use the overlap of control regimes for buck mode and boost mode, requiring a four-switch configuration and resulting in degraded efficiency in boost mode.
For a conventional slow converter, in which the control bandwidth (the bandwidth of the compensator and output filter) is much less than the switching frequency, the output filter may be relied upon to suppress any resulting variations in the output voltage. However, when a DC-DC converter is used as an envelope tracking power supply for a radio-frequency power amplifier (RF PA), it is necessary that the output voltage of the converter vary fast enough to provide the required voltage for each symbol to be transmitted through the RF PA, or in the case of wide-bandwidth modulations like orthogonal frequency-division multiplexing (OFDM), fast enough to follow the pseudo-random variation in output transmitted power. In modern communications standards, such as WCDMA or LTE, transmit bandwidths of 3.8, 5, 10, or even 20 MHz can be used. To keep the switching frequency as low as possible for best efficiency, the output filter is configured to allow passage of voltage variations at frequencies as high as fSW/6 or even fSW/4. Under these conditions, oscillations in the operation of the converter will appear as variations in the voltage supplied to the RF PA. Such variations may be converted into variations in the amplitude of the transmitted signal, leading to undesired (spurious) transmitter output at frequencies offset from the carrier by the frequency of oscillation of the converter. The oscillations are of particular import when the bandwidth of the envelope tracking signal is smaller than the oscillation frequency, so that the output voltage of the converter is roughly constant for a sufficient time for oscillations to occur.
Therefore, in a DC-DC converter used as an envelope tracking power supply, it is desirable to have means to suppress oscillations at very high duty cycle, while preserving the ability to modulate the output voltage in conformance with a rapidly-varying requested supply voltage to permit efficient operation of an RF power amplifier.